confused?

[ikhayriyyah]

i have a question??? Say I have pc who's processor works at 400 MHz, is not pipelines, and requires an average of 4 cycles to execute each instruction, has cache memory that takes 1 processor cycle with a miss ratio of 90%, when a cache miss occurs, it accesses regular memory, and each access takes 10 processor cycles, the processor contains 16 registers, and when interrupt occurs the processor saves all 16 registers onto the stack, all the sensors are connected to I/O controllers, and every time a sensor detects a failure condition, it instantly activates a bit inside the I/O controller, which passes on this condition on an interrupt signal that goes to the PIC(interrupt prioroty encoder
), then to the processor. The key requirement that i want of this system is that the time taken by the processor to respond to a sensor "failure condition" signal and execute the first instruction of the interrupt routine associated with that sensor must take less than 1 micro second. Does this pc system satisfy this requirement??? can you help me understand why??? i'm confused

[ikhayriyyah]

correction it's the hit ratio of 90% not the miss ratio...sorry about that.

[DNAunion2000]

Maybe not too much help, but...

As far as the period of one processor cycle, at 400 MHz the period is (1/400,000,000) sec, or 1 sec / 4 x 10^8 cycles, or 0.0025 microseconds.

As far as memory access is concerned, 90% of the time it gets a cache hit requiring just 1 cycle; the other 10% of the time it gets a cache miss and takes 10 cycles. So on average, it takes (0.90 x 1) + (0.10 x 10) = 1.9 processor cycles per memory access.

On average it would take (1.9 cycles/access) x (1 sec/4 x 10^8 cycles) = 0.475 x 10^-8 = 4.75 nanoseconds per memory access. That comes to 0.00475 microseconds.

As far as how long a single instruction takes....you said it takes 4 cycles per instruction. Since the CPU gets in 400 million cycles per second, then the rate is 100 million instructions per second (looking only at instructions). The reciprocal of that is the time period per instruction, or 0.01 microseconds.

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You could play with these numbers a bit. For example, if you assume that on average a single instruction requires two memory accesses, then the total time per instruction, including memory access, would be 0.01 + (2 x 0.00475) microseconds = 0.0195 microseconds. You could squeeze in 51 such instructions and still remain under the 1 microsecond limit.